Formal semantics and proof techniques for optimizing VHDL models
Umamageswaran, Kothanda
Formal semantics and proof techniques for optimizing VHDL models - Boston Kluwer Academic Publishers 1999 - 158
792383753
VHDL
621.392 UMA/F
Formal semantics and proof techniques for optimizing VHDL models - Boston Kluwer Academic Publishers 1999 - 158
792383753
VHDL
621.392 UMA/F