Formal semantics and proof techniques for optimizing VHDL models (Record no. 1302)

MARC details
000 -LEADER
fixed length control field 00450nam a2200157Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 130318s9999 xx 000 0 und d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 792383753
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392 UMA/F
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Umamageswaran, Kothanda
245 ## - TITLE STATEMENT
Title Formal semantics and proof techniques for optimizing VHDL models
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc. Kluwer Academic Publishers
Place of publication, distribution, etc. Boston
Date of publication, distribution, etc. 1999
300 ## - PHYSICAL DESCRIPTION
Extent 158
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element VHDL
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Pandey, Sheetanshu L
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Wilsey Philip A
Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Shelving location Date acquired Cost, normal purchase price Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
        Kerala University of Digital Sciences, Innovation and Technology Knowledge Centre Kerala University of Digital Sciences, Innovation and Technology Knowledge Centre Applied Electronics 18/03/2013 7214.00   621.392 UMA/F 1309 18/03/2013 18/03/2013 Books